Modern semiconductor devices are built on a silicon substrate that has P.sup.+ and N.sup.+ type doped regions in the substrate as basic elements of the device that must be connected in a specific configuration to form a desired circuit. The circuit must then be accessible to the outside world through conducting pads for testing and through bonding into a packaged chip. To form a semiconductor circuit, at least one layer of a conducting material such as metal or heavily-doped polysilicon must be deposited and patterned to form contacts and interconnects between the different regions of the chip. For instance, in a typical semiconductor fabrication process, a wafer is first covered with an insulating layer, patterned and etched for contact windows (or openings) in the insulating layer, and then a conductive material is deposited and defined to form contact plugs and interconnecting leads.
Contacts to silicon or silicide are usually defined and etched in an insulating layer, i.e., a dielectric layer, by using lithographic and dry etching techniques. A dry etching technique works anisotropically to enable the making of contact openings that have high aspect ratio and fairly vertical sidewalls. Contact openings are usually filled with a conducting material such as a metal or a heavily-doped polysilicon to form vertical connections to a first level metal. Polysilicon, when used as contact plugs, must be doped N type when contacting N-regions and P type for contacting P-regions in order to avoid inter-diffusion and dopant compensation. A polysilicon film can be doped during deposition, i.e., in-situ doping, by adding arsine, phosphine or diborane to a gas mixture when a film is deposited at low pressure in a pyrolitic decomposition process of silane at approximately 600.degree. C. Polysilicon film can also be doped after deposition by an ion implantation process or by a diffusion process. Most widely used applications of polysilicon is in metal-oxide-semiconductor (MOS) ICs. For instance, heavily-doped polysilicon films are frequently used as gate electrodes and interconnections in MOS circuits. The wide utility of polysilicon stems from its high compatibility with subsequent high-temperature processes, its excellent interface with thermal oxide, its high stability when compared to aluminum gate material, its high conformability over steep topography during deposition, and its ability to form silicide structures with an overlaying metal.
When polysilicon is used in contact plugs, it is usually formed in a dielectric layer which separates a multiplicity of plugs, interconnects and circuits. In order to form a contact plug, a contact window or opening must be first formed in the dielectric layer by selective etching to expose portions of the underlying circuit or a lower interconnect layer. After polysilicon is deposited into the contact window, it connects the lower interconnect layer to an upper interconnect layer that is subsequently deposited on top of the interlayer dielectric material. The contact window can be made in an etching process of either wet etch or dry etch. A wet etch process is performed by immersing the wafers in an appropriate etchant solution or by spraying the wafers with the solution. When a wet etch process is conducted, the etching action is isotropic in nature so that the material is etched in both the lateral and the vertical directions. Lateral etching in a wet etch process produces undercutting under a mask which is undesirable in most fabrication processes. On the other hand, a dry etch process etches anisotropically and creates vertical sidewalls in a contact window such that the top and the bottom of the window have almost the same dimensions. The dry etch process is preferred in modern sub-micron devices since it does not create undercutting problem and does not require or waste additional lateral area for a contact window. The dry etching technique also provides the benefits of reduced chemical hazard and waste treatment problems, and easily achievable process automation and tool clustering. Two of the most widely used dry etching techniques are the plasma etching technique and the reactive ion etching technique.
While dry etching technique provides significant improvement in dimensional control and therefore is popular in VLSI and ULSI fabrication methods, it also has some drawbacks. One of the drawbacks is that due to the anisotropic nature of the etching process, substantially vertical sidewalls are produced in a contact window when formed by a dry etching process. The vertical sidewalls in the contact window lead to a problem of filling the window in a subsequent deposition process for an upper interconnect layer. The problem becomes more severe as the device dimensions are further reduced and thus contact windows of even higher aspect ratios are required. For instance, when an interconnect layer of a conductive material is subsequently deposited by a conventional deposition method, particles of the conductive material cannot conform to the contours of the contact window especially at steps or sharp corners. As a result, a thinner then desired conductive material layer or a void can be formed in the contact plug. The thin conductive material layer or the void results in defects in the IC device fabricated.
Others have attempted to solve the contact window filling problem by various proposals. For instance, a method disclosed in U.S. Pat. No. 4,698,128 utilizes a modified dry etch process which creates a stepwise sloped sidewall of the contact window. However, the process requires a time consuming dry etch cycle and is not desirable in etching vias in thick dielectric layers. Another attempt, as illustrated in U.S. Pat. No. 4,902,377 is made in forming a via by separate wet and dry etching processes. In this method, a top portion of a via is first formed by a dry etching process which isotropically undercuts the masking film to create a sloped sidewall. A bottom portion of the via is then formed by a dry etching process including alternating steps between a number of isotropic mask erosion steps and a number of anisotropic dielectric etching steps. The process is difficult to carry out and requires numerous processing steps that are both labor intensive and time consuming.
It is therefore an object of the present invention to provide a method for forming a tapered polysilicon plug that does not have the drawbacks or shortcomings of the conventional plug forming techniques.
It is another object of the present invention to provide a method of forming a tapered polysilicon plug which only requires the use of a dry etching technique in forming a contact window.
It is a further object of the present invention to provide a method of forming a tapered polysilicon plug by first forming at least two polysilicon sidewall spacers in a contact window and anisotropically etching the dielectric layer such that a contact window having a sloped opening is formed.
It is still another object of the present invention to provide a method of forming a tapered polysilicon plug by repeatedly depositing and anisotropically etching away polysilicon layers such that polysilicon sidewall spacers are formed as part of a tapered polysilicon plug that is subsequently deposited.
It is yet another object of the present invention to provide a method of forming a tapered polysilicon plug by depositing and forming polysilicon sidewall spacers and then using the spacers as masks to etch away anisotropically a dielectric material that the plug is formed therein.
It is another further object of the present invention to provide a tapered polysilicon plug in a dielectric layer that has a main plug body and at least one polysilicon sidewall spacer surrounding the plug body at or near the upper end of the plug.
It is still another further object of the present invention to provide a tapered polysilicon plug that is formed in a dielectric layer including a plug body and at least two polysilicon sidewall spacers surrounding the plug body adjacent the upper end of the plug wherein the plug is deposited of a doped polysilicon material.